Change Vd and Vgs via the sliders below, and observe the field buildup inside the device and the accompanying parametric changes.
This interactive simulation was written to gain an understanding of transconductance (or Gm).
When is it fixed?, When does it vary?
Parametric (or Etest) testing sweeps the
Vgs (gate to source) voltage for a given Vd (drain) voltage, to derive the (curve sweep) plot on the right.
The transistor does not " Turn-on " (or conduct current through the drain = Id) until Vgs reaches the " Threshold Voltage " (or Vt).
Note that Vd changes only effect Id in the " Linear " region
(hence " Saturation " means Vd changes do not effect the Id current flow through the transistor).
Vd (the drain voltage, or voltage across the whole transistor) must be less than
Vgs (the gate to source voltage) - Vt (the theshold or turn on voltage) to be in this (ohmic or) linear region.
Low Vds puts you are in linear region - where analog design
engineers use the transistor as an amplifier (to make incoming signals bigger) or attenuator (to make incoming signals smaller).
It is a small signal in that region but analog engineers
are not concerned with the power characteristics of the transistor -
only the linearity. They will then add input and output stages to the
transistor to get an amplifier (the transistor itself is not very useful
by itself for amplication) to handle power and load issues.
Digital design engineers only operate
in saturation and mostly care about the capacitance and speed of the
transistor.
Normally the source and bulk Silicon substrate are grounded (or at least they are at the same potential).
If there is a Vsb between the source and the bulk (Silicon substrate), the
Vt (threshold) voltage is affected .
If this does not make sense to you, please see
Semiconductor Basics under Ken's Technology Notes
(for an explaination of how transistors are used in analog amplifier and digital circuits).